資料庫
| 時間 | 議題 | 附件 |
| 03/17, 2020 | Online Peak-to-Peak Jitter Monitoring for A Phase-Locked Loop - 清華大學 |  |
| 04/21, 2020 | TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning - 中山/中興大學 | |
| 05/19, 2020 | A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability - 交通大學 | |
| 06/16, 2020 | SAFER:Single Aging Factor Enhanced Rings for Data Annotation & Early Warning in Online Aging Monitor of Automotive SoCs Precompensation, BIST and Analogue Berger Codes for Multi-level Writing RRAM - 彰化師範大學 |
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| 11/27, 2020 | DLL-Based Thermal Sensor - 清華大學 | |
| 12/25, 2020 | PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques - 中山/中興大學 | |
| 01/22 2021 | Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop - 交通大學 | |
| 03/26 2021 | Process Resilient Fault-Tolerant Delay-Locked Loop Using TMR with Dynamic Timing Correction - 清華大學 | |
| 08/13 2021 | Rigorous Test Flow for PLL using Jitter Measurement with VDD Sweeping - 清華大學 | |
| 03/11 2022 | A Just-Enough Stress Test Methodology to Support Infant-Mortality Fault Screening and Multi-Stress-Level Based Lifetime Prediction for Safety Critical IC Products - 清華大學 | |