【Roadmap】

  The figure below streamlines the research topics to be investigated in a typical test and operation flow from wafer-level test, final test, to safety-aware field operation. All the design-for-testability/testing/monitoring/self-healing schemes throughout this flow contributes to our final two goals – zero failure rate and long lifetime. It is notable that this project plans to leverage on, not recreate, traditional methods, such as ATPF for various fault types, Built-In Self-Test (BIST), speed binning to screen out weak devices, and Built-In Self-Repair (BISR). What we plan to develop are complimentary test/monitoring/self-healing technologies to these previous traditional methods, as detailed below: