專書與章節

1. S.-Y. Huang, and K.-T. Cheng, "Formal Equivalence Checking and Design Debugging", Kluwer Academic Publishers, (June, 1998)
2. S.-Y. Huang, Chapter 7 - Logic Diagnosis of "VLSI Test Principles and Architectures - Design for Testability," Edited by L.-T. Wang, C.-W. Wu, and X. Wen, Morgan Kaufmann Publishers, pp. 397-460, (June 2006).
3. S.-Y. Huang, "Interconnect Testing for 2.5D- and 3D-SICs", A Chapter in Handbook of 3D Integration, Vol. 4, Edited by Ramm, Garrou, Koyanagi, Franzon, Franzon, Marinissen and Bakir, Wiley-VCH, ISBN: 978-3-527-33855-9, (March 2019).