著作

 
專書與章節
期刊
 會議論文集 專利

期刊


  1. S.-Y. Huang and K.-T. Cheng, "ErrorTracer: A Fault-Simulation-Based Approach to Design Error Diagnosis", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1341-1352, (Sept. 1999).
  2. S.-Y. Huang, K.-C. Chen and K.-T. Cheng, "AutoFix: A Hybrid Tool for Automatic Logic Rectification", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1375-1384, (Sept. 1999).
  3. K.-T. Cheng, S.-Y. Huang, and W.-J. Dai, "Fault Emulation: A New Methodology for Fault Grading," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1487-1495, (Oct. 1999).
  4. S.-Y. Huang, K.-T. Cheng, K.-C. Chen, C.-Y. Huang, and F. Brewer, "AQUILA: An Equivalence Checking System for Large Sequential Designs," IEEE Trans. on Computers, pp. 443-464, (May 2000).
  5. S.-Y. Huang, K.-T. Cheng, K.-C. Chen, "Verifying Sequential Equivalence Using ATPG techniques," ACM Trans. on Design Automation of Electronic Systems, pp. 244-275, (April 2001).
  6. S.-Y. Huang, D.-M. Kwai, and C. Huang, "A High-Speed Architecture For At-Speed DRAM Testing," Journal of The Chinese Institute of Electrical Engineering, Vol. 8, No. 4, pp. 387-394, (Nov. 2001).
  7. S.-Y. Huang, "Improving the Timing of Extended Finite State Machines Via Catalyst," VLSI Design Journal, Vol. 15, No. 3, pp. 629-636, (Nov. 2002).
  8. S.-Y. Huang, "A Symbolic Inject-And-Evaluate Paradigm for Byzantine Fault Diagnosis," Journal of Electronic Testing, Theory and Applications (JETTA), Vol. 19, No. 2, pp. 161-172, (April 2003).
  9. H.-C. Kao, M.-F. Tsai, S.-Y. Huang, C.-W. Wu, W.-F. Chang, and S.-K. Lu, "Efficient Double Fault Diagnosis for CMOS Logic Circuits With A Specific Application To Generic Bridging Faults," Journal of Information Science and Engineering (JISE), Vol. 19, No. 4, pp. 571-586, (July 2003).
  10. S.-Y. Huang and C.-J. Liu, "A Low-Power Architecture For Extended Finite State Machines Using Input Gating," IEICE Trans. on Fundamentals, Vol. E87-A, No. 12, pp. 3109-3115, (Dec. 2004).
  11. Y.-J. Juang, S.-F. Chen, S.-Y. Huang, Y.-C. King, "A Low-Cost Logarithmic CMOS Image Sensor Design By Nonlinear Analog-To-Digital Conversion," IEEE Trans. on Consumer Electronics, Vol. 51, No. 4, pp. 1212-1217, (Nov. 2005).
  12. K.-H. Lai, S.-Y. Huang, and P.-C. Chiang, "A Sizing Methodology for the Charge Noise Reduction of a Comparator," Int'l Journal of Electrical Engineering, Vol. 13, No. 1, pp. 1-7, (Feb. 2006).
  13. C.-H. Lai, Y.-C. King, and S.-Y. Huang, "A 1.2V 0.25um Clock Output Pixel Architecture With Dynamic Range and Self-Offset Cancellation," IEEE Sensors Journal,, Vol. 6, No. 2, pp. 398-405 (April 2006).
  14. Y.-C. Lin and S.-Y. Huang, "Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 22, No. 2, pp. 151-159, (April 2006).
  15. Y.-T. Lin and S.-Y. Huang, "Low-Power Adaptive FIR Filter Generator Using Bit-Oriented Structures," IEE Proceedings Circuits, Devices, and Systems, Vol. 153, No. 2, pp. 167-172, (April 2006).
  16. H.-B. Wang, S.-Y. Huang, and J.-R. Huang, "A Modified Inject-and-Evaluate Paradigm for Diagnosing Gate-Delay Faults," Int'l Journal of Electrical Engineering, Vol. 13, No. 2, pp. 185-191, (May 2006).
  17. C.-W. Tzeng and S.-Y. Huang, "Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain," IEEE Trans. on Circuits and Systems II: Express Briefs (TCAS-II), Vol. 54, No. 8, pp. 690-694, (Aug. 2007).
  18. C.-F. Chen, S.-Y. Huang, and Y.-C. King, "Built-In Self-Repair for Die-to-Die Misalignment for Multi-Die Space Sensors," IEEE Sensors Journal, Vol. 7, No. 9, pp. 1354-1355, (Sept. 2007).
  19. C.-W. Tzeng, J.-J. Hsu, and S.-Y. Huang, "A Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains," IET Proc. on Computers and Digital Techniques, Vol. 1, No. 6, pp. 706-715, (Nov. 2007).
  20. C.-W. Tzeng, J.-S. Yang, and S.-Y. Huang, "A Versatile Paradigm for Scan Chain Diagnosis of Complex Faults Using Signal Processing Techniques," ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 13, No. 1, pp. 9.1-9.27, (Jan. 2008).
  21. C.-W. Tzeng and S.-Y. Huang, "UMC-Scan Test Methodology - Exploiting the Maximum Freedom of Multicasting," IEEE Design and Test of Computers (D&T), Vol. 25, No. 2, pp. 132-140, (March-April, 2008).
  22. S.-P. Cheng and S.-Y. Huang, "A Low-Power SRAM for Viterbi Decoder in Wireless Communication," IEEE Trans. on Consumer Electronics, Vol. 54, No. 2, pp. 290-295, (May 2008).
  23. Y.-C. Lai and S.-Y. Huang, "X-Calibration: A Robust Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs," IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 9, pp. 1964-1971, (Sept. 2008).
  24. Y.-C. Lai and S.-Y. Huang, "A Resilient and Power Efficient Automatic-Power-Down Sense Amplifier for SRAM Design," IEEE Trans. on Circuits and Systems II: Express Briefs (TCAS-II), Vol. 55, No. 10, pp. 1031-1035, (Oct. 2008).
  25. Y.-C. Lai and S.-Y. Huang, "Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)," IEEE Journal of Solid-State Circuits (JSSC), Vol. 44, No. 2, pp. 642-649, (Feb. 2009).
  26. C.-W. Tzeng, H.-C. Cheng, and S.-Y. Huang, "Layout-Based Defect-Driven Diagnosis for Intra-Cell Bridging Defects," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 5, pp. 764-769, (May 2009).
  27. Y.-C. Lai, S.-Y. Huang, and H.-J. Hsu, "Resilient Self-VDD-Tuning Scheme with Speed Margining for Low-Power SRAM," IEEE Journal of Solid-State Circuits (JSSC), Vol. 44, No. 10, pp. 2817-2823, (Oct. 2009).
  28. C.-W. Tzeng and S.-Y. Huang, "QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 11, pp. 1756-1766, (Nov. 2009).
  29. C.-W. Tzeng and S.-Y. Huang, "Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture with Test Compression," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, pp. 834-839, (May 2010).
  30. C.-H. Lo and S.-Y. Huang, "P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Sub-Threshold Operation," IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 3, pp. 695-704, (March, 2011).
  31. Bor-Woei Kuo, Hsun-Hao Chang, Yung-Chang Chen, and Shi-Yu Huang, "A Light-and-Fast SLAM Algorithm for Robots in Indoor Environments Using Line Segment Map," Journal of Robotics, (WEB-LINKING) Volume 2011, Article ID 257852, 12 pages, (2011).
  32. S.-K. Lu, Y. Chen, S.-Y. Huang, and C.-W. Wu, "Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores," IEEE Design & Test of Computers (D&T), Vol. 28, No. 4, pp. 88-97, (July-Aug. 2011).
  33. H.-J. Hsu and S.-Y. Huang, "A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme," IEEE Trans. on VLSI Systems (TVLSI), Vol. 17, No. 11, pp. 165-170, (Nov. 2011).
  34. F.-C. Huang, S.-Y. Huang, J.-W. Ker, and Y.-C. Chen, "High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction," IEEE Trans. on Circuits and System for Video Technology (TCAS-VT), Vol. 22, No. 3, pp. 340-351, (March 2012).
  35. T.-Y. Li, S.-Y. Huang, H.-J. Hsu, C.-W. Tzeng, C.-T. Huang, J.-J. Liou, H.-P. Ma, P.-C. Huang, J.-C. Bor, C.-C. Tien, and M. Wang, and C.-W. Wu, "AC-Plus Scan Methodology for Small Delay Testing and Characterization," IEEE Trans. on VLSI Systems (TVLSI), Vol. 21, No. 2, pp. 329-341, (Feb. 2013).
  36. J.-W. You, S.-Y. Huang, Y.-H. Lin, M.-H. Tsai, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis," IEEE Trans. on VLSI Systems (TVLSI), Vol. 21, No. 3, pp. 443-453, (March 2013).
  37. J.-W. Ke, S.-Y. Huang, C.-W. Tzeng, D.-M. Kwai, and Y.-F. Chou, "Die-to-Die Clock Synchronization for 3D IC using Dual Locking Mechanism," IEEE Trans. on Circuits and Systems - Part I (TCAS-I), Vol. 60, No. 4, pp. 908-917, (April 2013).
  38. Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, "Parametric Delay Test of Post-Bond TSVs in 3-D ICs via VOT Analysis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 5, pp.-737-747, (May 2013).
  39. S.-Y. Huang, Y.-H. Lin, Li-Ren Huang, K.-H. Tsai, and W.-T. Cheng, "Programmable Leakage Test and Binning for TSVs with Self-Timed Timing Control," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 8, pp. 1265-1273, (Aug. 2013).
  40. L.-R. Huang, S.-Y. Huang, S. Sunter, K.-H. Tsai, and W.-T. Cheng "Oscillation-Based Pre-Bond TSV Test," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Vol. 32, No. 9, pp. 1440-1444, (Sept. 2013).
  41. R.-T. Ding, S.-Y. Huang, and C.-W. Tzeng, "Cell-Based Process Resilient Multi-Phase Clock Generation," IEEE Trans. on VLSI Systems (TVLSI), Vol. 21, No. 12, pp.2348-2352, (Dec. 2013).
  42. P.-Y. Chao, C.-W. Tzeng, S.-Y. Huang, C.-C. Weng, and S.-C. Fang, "Process Resilient Low-Jitter All-Digital PLL via Smooth Code Jumping," IEEE Trans. on VLSI Systems (TVLSI), Vol. 21, No. 12, pp. 2240-2249, (Dec. 2013).
  43. L.-R. Huang, S.-Y. Huang, K.-H. (Hans) Tsai, and W.-T. Cheng, "Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 3, pp. 476-488, (March 2014).
  44. C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, "Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration," IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, (March 2014).
  45. S.-Y. Huang, J.-Y. Lee, K.-H. (Hans) Tsai, and W.-T. Cheng, "Pulse-Vanishing Test for Interposers Wires in 2.5-D IC," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 8, pp. 1258-1268, (Aug. 2014).
  46. S.-Y. Huang and Li-Ren Huang, "PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning," IEEE Design and Test (D&T), Vol. 31, No. 4, pp. 36-42, (Aug. 2014).
  47. C.-Y. Lin, C.-W. Huang, C.-B. Kuan, S.-Y. Huang, and J.-K. Lee, "The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multi-Core Systems," ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 20, No. 2, Article 22, (Feb. 2015).
  48. S.-Y. Huang, M.-T. Tsai, Z.-F. Zeng, K.-H. (Hans) Tsai, and W.-T. Cheng, "General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No 11, pp. 1836-1846, (Nov. 2015).
  49. S.-Y. Huang, M.-T. Tsai, H.-X. Li, Z.-F. Zeng, K.-H. (Hans) Tsai, and W-.T. Cheng, "Non-Intrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No 12, pp. 2039-2048, (Dec. 2015).
  50. S.-Y. Huang, M.-T. Tsai, K.-H. (Hans) Tsai, and W.-T. Cheng, "Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects," IEEE Design and Test (D&T), Vol. 33, No. 2, pp. 9-16, (April 2016).
  51. S.-T. Tseng, Y.-H. Kao, C.-C. Peng, J.-Y. Liu, S.-C. Chu, G.-F. Hong, C.-H. Hsieh, K.-T. Hsu, W.-T. Liu, Y.-H. Huang, S.-Y. Huang, and T.-S. Chu, "A 65nm CMOS Low-Power Impulse Radar System for Human Respiratory Feature Extraction and Diagnosis on Respiratory Diseases," IEEE Transactions on Microwave Theory and Techniques, Vol. 64, No. 4, pp. 1029-1041, (April 2016).
  52. S.-Y. Huang, C.-C. Cheng, M.-T. Tsai, K.-C. Huang, K.-H. Tsai, and W.-T. Cheng, "Versatile Transition-Time Monitoring for Interconnects via Distributed TDC," IEEE Design and Test (D&T), Vol. 33, No. 6, pp. 23-30, (Nov. 2016).
  53. S.-F. Yang, Z.-Y. Wen, S.-Y. Huang, K.-H. Tsai, and W.-T. Cheng, "Circuit and Methodology for Testing Small Delay Faults in the Clock Network," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 37, No. 10, pp. 2087-2097, (Oct. 2018).
  54. Z.-H. Zhang, W. Chu and S.-Y. Huang, "A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Dealy-Locked Loop," IEEE Access, Vol. 7, pp. 97928-97937, (July 2019).
  55. G.-H. Lian, W.-Y. Chen, and S.-Y. Huang, "Cloud-Based Online Ageing Monotoring for IoT Devices," IEEE Access, Vol. 7, pp. 135964-135971, (Sept. 2019).
  56. C.-H. Wu, S.-Y. Huang, Y.-F. Chou, and D.-M. Kwai, "Time-to-Digital Converter Compiler for On-Chip Instrumentation," IEEE Design and Test (D&T), Vol. 37, No. 4, pp. 101-107, (Aug. 2020).
  57. M. Chern, S.-W. Lee, S.-Y. Huang, Y. Huang, G. Veda, K.-H. (Hans) Tsai, and W.-T. Cheng, "Diagnosis of Intermittent Scan Chain Faults Through a Multi-Stage Neural Network Reasoning Process," IEEE Trans. on Computer-Aided Design ofIntegrated Circuits and Systems (TCAD), Vol. 39, No. 10, pp. 3044-3055, (Oct. 2020).
  58. W. Chu and S.-Y. Huang, "Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor," IEEE Trans. on Emerging Topics in Computing (TETiC), Vol. 9, No. 2, pp. 735-744, (April-June, 2021).
  59. J.-Y. Yang and S.-Y. Huang, "Process Resilient Fault Tolerant Delay Locked Loop using TMR with Dynamic Timing Correction," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 41, No. 5, pp. 1563-1572, (May 2022).
  60. J.-Y. Yang and S.-Y. Huang, "A Tiny Monitor for Fault and Soft-Error Tolerant DLL To Support Graceful Degradation and Module-level Testing," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 41, No. 7, pp. 2337-2347, (July 2022).
  61. W.-H. Chen and S.-Y. Huang, "On-Chip Jitter Learning for PLL," IEEE Design and Test (D&T), Vol. 39, No. 4, pp. 58-63, (Aug. 2022).
  62. Y.-C. Su and S.-Y. Huang, "Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 2761-2765, Vol. 42, No. 8, (Aug. 2023).
  63. L. Lin, C. Lai, S.-Y. Huang and K.-Y. Yeh, "Compiler of Reed-Solomon Codec for 400 Gbps IEEE 802.3bs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 2776-2780, Vol. 42, No. 8, (Aug. 2023).
  64. Y.-C. Su and S.-Y. Huang, "A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells," IEEE Trans. on VLSI Systems (TVLSI), Vol. 31, No. 3, pp. 343-354, (March 2023).
  65. S.-H. Yang and S.-Y. Huang, "General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR Using A Synchronization-before-Voting Scheme," Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 40, No. 1, (Feb. 2024).
  66. C.-Y. Wen and S.-Y. Huang, "Instant Test and Repair for TSVs Using Differential Signaling," Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 40, No. 2, (April 2024).
  67. S.-Y. Chang and S.-Y. Huang, "A Check-and-Balance Scheme in Multi-Phase Delay Locked Loop," accepted to appear in IEEE Trans. on VLSI Systems (TVLSI), (2024).
  68. K.-H. Lin, O-D. Lin, S.-Y. Huang, and D. Sheng, "Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment," (Accepted to appear), IEEE Trans. on VLSI Systems (TVLSI), (2024).