General Direction:
The research interests of this lab broadly cover VLSI design, automation, and testing, with prior experiences on formal verification, power estimation, fault diagnosis, and resilient nanometer SRAM Design. More recently, it is more concentrated on All-digital timing circuit designs, such as all-digital phase-locked loop (PLL), all-digital delay-locked loop (DLL), time-to-digital converter (TDC), and their applications to parametric fault testing for interconnects. From this lab, two research achievements including “eClock – a cell-based PLL compiler” and “PowerMixer – a multi-level power estimation software tool” were ever made commercial products.

Current research projects:

1. Cell-Based Timing Circuits and Their Compilers Design


2. Delay Monitoring for Die-to-Die Interconnects in Multi-Die ICs


3. Scan Chain Diagnosis using Machine Learning Techniques


4. DART (Data-Assisted Reliability and Testing for VLSI)

Previous research projects:

1. High-Yield SRAM Design for Nanometer Technology


2. All-Digital PLL and Its Compiler


3. SoC Multi-Core Power Estimation Tools


4. Quick & Cool Scan Test Methodology


5. Parametric Fault Testing for Die-to-Die Interconnects in 3D-IC

Updated: Sept. 3,2018