Program
2017 ITC-Asia Program At A Glance (with Hyperlinks)
Sept. 13 – Wednesday, 13:30-16:50 am Half-Day Tutorials Session Chair: (TBD) |
To be provided by speaker.
Biography

Abstract
After a long period of technology hype, finally real 3D-stacked IC products containing through-silicon vias and micro-bumps (and also their interposer-based 2.5D-SIC variant) are hitting the market. Testing of 2.5D- and 3D-SICs is fraught with new test and design-for-test challenges, for which solutions are only emerging. The test challenges are the following. (1) Test flows: what to test for when? (2) Test content: do these stacked ICs bring new defects and faults and how do we test for those? (3) Test access: how do we pump in/out the test stimuli/responses into the dies and die stacks? In this tutorial, we present the fundamentals of 3D fabrication processes, defects, and fault modeling. We discuss test flows and present test-flow cost modeling and optimization. The tutorial covers the most promising solutions for pre-bond and post-bond (stack) testing, including advances in 3D probe technology, advanced 3D-DfT architectures and optimization, and the ongoing IEEE P1838 standardization effort for test access.
Biography

Abstract
To be provided by the speaker.
Biography

Sept. 14 – Thursday, 9:00-10:40 am Keynote (I) Session Chair: (TBD) |
In this talk I will illustrate several types of Hardware Trojans and security threats they create, as well as opportunities of Trojan insertion in all steps of the design, fabrication, and testing processes. I will then discuss their defense mechanisms, verification techniques for Trojan detection and prevention, and test-specific need and challenges for hardware security.
Biography

Cheng, an IEEE fellow, received 10+ Best Paper Awards from various IEEE and ACM conferences and journals. He has also received UCSB College of Engineering Outstanding Teaching Faculty Award. He served as Editor-in-Chief of IEEE Design and Test of Computers and was a board member of IEEE Council of Electronic Design Automation’s Board of Governors and IEEE Computer Society’s Publication Board.
Abstract
To be provided by the speaker.
Biography
To be provided by the speaker.
Sept. 15 – Thursday, 9:00-10:30 am Keynote (II) Session Chair: (TBD) |
To be provided by the speaker.
Biography

Abstract
To be provided by the speaker.
Biography

Sept. 14 – Thursday, 11:00-12:20 am Plenary Panel Panel Chair: Prof. Cheng-Wen Wu |
Sept. 14 – Thursday, 13:30-14:45 pm Session A1: (Invited) Corporate Session (I) Session Chair: (TBD) |
A1-1:
To be designed…
A1-2:
To be designed…
A1-3:
To be designed…
Sept. 14 – Thursday, 13:30-14:45 pm Session B1: Analog and Mixed-Signal Test Session Chair: (TBD) |
B1-1:
Low-Distortion Signal Generation for Analog/Mixed-Signal Circuit Testing with Digital ATE
Masayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida and Haruo Kobayashi
B1-2:
A Quick Jitter Tolerance Estimation Technique for Bang-bang CDRs
Yen-Long Lee and Soon-Jyh Chang
B1-3:
Evaluation of Loop Transfer Function Based Dynamic Testing of LDOs
Mehmet Ince, Sule Ozev, Ender Yilmaz, Jae Woong Jeong and Leroy Winemberg
Sept. 14 – Thursday, 13:30-14:45 pm Session C1: Cell-Aware Test Session Chair: (TBD) |
C1-1:
(invited) The Role of Test in Advanced System Design – Challenges & Opportunities
Rob Knoth, Cadence
C1-2:
Test Generation for Open and Delay Faults in CMOS Cells
Cheng-Hung Wu, Kuen-Jong Lee and Sudhakar M. Reddy, National Cheng-Kung Univ., Taiwan
C1-3:
Cell-Aware Test Time Reduction by Using Switch-Level ATPG
Po-Yao Chuang, Cheng-Wen Wu and Harry H. Chen, National Tsing Hua Univ., Taiwan
Sept. 14 – Thursday, 15:00-16:40 pm Session A2: (Invited) Corporate Session (II) Session Chair: (TBD) |
A2-1:
To be designed…
A2-2:
To be designed…
A2-3:
To be designed…
Sept. 14 – Thursday, 15:00-16:40 pm Session B2: Detection, Diagnosis, and Debugging Session Chair: (TBD) |
B2-1:
GPU Accelerated Fault Dictionary Generation for the TRAX Fault Model
Matthew Beckler and Shawn Blanton, Carnegie Mellon Univ., USA
B2-2:
Physical-aware Diagnosis of Multiple Interconnect Defects
Jing-Yu Chen, Po-Hao Chen, Chi-Lin Lee, Po-Wei Chen, and Chien-Mo Li, National Taiwan Univ., Taiwan
B2-3:
A Run-Pause-Resume Silicon Debug Technique for Clock Domain
Shuo-Lian Hong and Kuen-Jong Lee, National Cheng-Kung Univ., Taiwan
B2-4:
A Hybrid Concurrent Error Detection Scheme for Simultaneous Improvement on Probability of Detection and Diagnosability
Chih-Hao Wang and Tong-Yu Hsieh, National Sun Yat-Sen Univ., Taiwan
Sept. 14 – Thursday, 15:00-16:40 pm Session C2: Test for IoT and Automotives Session Chair: (TBD) |
C2-1:
A Dependable AMR Sensor System for Automotive Applications
Andreina Zambrano and Hans Kerkhoff
C2-2:
An Automotive MP-SoC Featuring an Advanced Embedded Instrument Infrastructure for High Dependability
Hans G. Kerkhoff, Ghazanfar Ali, Hassan Ebrahimi, and Ahmed Ibrahim
C2-3:
Symbiotic System Models for Efficient IOT System Design and Test
Cheng-Wen Wu, Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, and Chi Chen
C2-4:
A Lightweight X-Masking Scheme for IoT-Designs
Daniel Tille, Benedikt Gottinger, and Ulrike Pfannkuchen
Sept. 15 – Friday, 10:50-12:05 am Session A3: (Invited) EDA Session Session Chair: (TBD) |
A3-1:
To be designed…
A3-2:
To be designed…
A3-3:
To be designed…
Sept. 15 – Friday, 10:50-12:05 am Session B3: Test for InFO and SoC Session Chair: (TBD) |
B3-1:
Fan-Out Wafer Level Chip Scale Package Testing
Hao Chen, Hung-Chih Lin, and Min-Jer Wang
B3-2:
Testing-for-Manufacturing (TFM) for Ultra-thin IPD on InFO
Tang-Jung Chiu
B3-3:
(invited) Test Strategy for Storage SoCs
Abhishek Bhattacharya and Ramesh Tekumalla
Sept. 15 – Friday, 10:50-12:05 am Session C3: Memory Test Session Chair: (TBD) |
C3-1:
Adaptive Block-Based Refresh Techniques for Mitigation of Data Retention Faults and Reduction of Refresh Power
Shyue-Kung Lu
C3-2:
Software-Hardware-Cooperated Built-In Self-Test Scheme for Channel-Based DRAMs
Tsung-Fu Hsien, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, and Yung-Fa Chou
C3-3:
Adapting an Industrial Memory BIST solution for testing CAMs
Jais Abraham, Uttam Garg, Glenn Colon-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, and Martin Keim
Sept. 15 – Friday, 13:30-14:45 pm Session A4: (Invited) Fabless and IDM Session Session Chair: (TBD) |
A4-1:
(invited) DFT Challenges and Solutions for Automotive ICs
Ying-Yen Chen, RealTek Semiconductor Corp, Taiwan
Abstract: Compared to consumer ICs, automotive ICs have more stringent requirement including extremely high test coverage, short failure analysis time and the ability of in-field test and diagnosis. In this presentation, we will describe the challenges we faced and the solutions we took in DFT aspect of automotive ICs.
A4-2:
(invited) Multi-Pronged Strategy to Reduce Scan Test Cost at Advanced Process Nodes
Jianguo Ren, MediaTek Inc., Taiwan
Abstract: For advanced semiconductor processes, more and more fault models are required to improve chip quality, causing a dramatic rise in scan-related production test cost. We can address test cost reduction at three levels: design planning, chip implementation, and ATE execution. This talk will focus on chip implementation and ATE execution: (1) circuit modifications to increase scan shift frequency, and (2) constraining ATE timing sets to be speed-path and IR-drop aware. Adoption of these solutions has resulted in a 50% reduction of scan-related test cost across many products at MediaTek.
A4-3:
(invited) What do we do to make system reliable?
Xinli Gu, Huawei Technologies, USA
Abstract: A reliable system requires an end-to-end planning, design, manufacturing test and maintenance for reliability. The reliability challenges for a large system come from the followings: 1) new designs and technologies which haven’t been fully tested in the field, 2) extremely large number of pieces of designs that no single individual can fully understand its reliability coverage, 3) 3rd party or legacy designs/parts used in the system, and 4) complicated system operation environment in customer field. This presentation will cover the reliability challenges and the best industrial practice, and promote research to work on the methodology for industrial system reliability.
Sept. 15 – Friday, 13:30-14:45 pm Session B4: On-Chip Test Infrastructure Session Chair: (TBD) |
B4-1:
Reconfigurable Access to On-Chip Infrastructure
Michael Kochte, Rafal Baranowski, and Hans-Joachim Wunderlich
B4-2:
On the Effects of Real Time and Contiguous Measurement with a Digital Temperature and Voltage sensor
Yousuke Miyake, Yasuo Sato, and Seiji Kajihara
B4-3:
Enhancing Security of Logic Encryption Using Embedded Key Generation Unit
Rajit Karmakar, Santanu Chattopadhyay, and Rohit Kapur
Sept. 15 – Friday, 13:30-14:45 pm Session C4: Advanced Test Practices Session Chair: (TBD) |
C4-1:
A Mathematical Model to assess the influence of parallelism in a Semiconductor Back-End Test Floor
Davide Appello, Mariapina Laurino, and Marco Pranzo
C4-2:
A Full-Automatic Test System for Characterizing Large-Array Fine-Pitch Micro-Bump Probe Cards
Erik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Joerg Kiesewetter, Eric Hill, and Ken Smith
C4-3:
Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints
Young-Woo Lee, Inhyuk Choi, Kang-Hoon Oh, James Jinsoo Ko, and Sungho Kang
Sept. 15 – Friday, 15:00-16:40 pm Session A5: (Invited) OSAT Session Session Chair: (TBD) |
A5-1:
(invited) To be designed
Wendy Chen, KYEC, Taiwan
A5-2:
(invited) To be designed
Roger Huang, ASE, Taiwan
A5-3:
(invited) To be designed
George Chang, Chroma (ATE), Taiwan
A5-4:
(invited) A Probe Card Metrology Process Enabling Fast Feedback Loops to Reduce Operational and Maintenance Related cost
Martin Kunz, NanoFocus, Germany
Sept. 15 – Friday, 15:00-16:40 pm Session B5: Verification and Fault Tolerance Session Chair: (TBD) |
B5-1:
Assignment for Fault Tolerant Stochastic Computing with Linear Finite State Machines
Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki and Tomoo Inoue
B5-2:
An Integrated Design Environment of Fault Tolerant Processors with Flexible HW/SW Solutions for Versatile Performance/Cost/Coverage Tradeoffs
Yi-Ju Ke, Yi-Chieh Chen and Ing-Jer Huang
B5-3:
Speeding up Power Verification by Merging Equivalent Power Domains in RTL Design with UPF
Charles C.-H. Hsu and Charles H.-P. Wen
Sept. 15 – Friday, 15:00-16:30 pm Session C5: Embedded Tutorials Session Chair: (TBD) |
C5-1:
At-Speed Test Challenges for Giga-Size and Giga-Hertz Designs
Kun-Han (Hans) Tsai, Mentor Graphics, USA
Abstract: At-speed test is a must to ensure the high quality of today’s high performance ICs by screening out timing defects. This tutorial highlight the main challenges for testing today’s high performance designs with multiple cores and the state-of-art solutions in industrial designs.
C5-2:
Deep Neural Network Design and Applications on Testing
Jin-Fu Li, National Central Univ., Taiwan
C5-3:
To be designed
Charles Wen, National Chiao-Tung Univ., Taiwan