2017 ITC-Asia Program At A Glance (with Hyperlinks)

Sept. 13 - Wednesday Sept. 14 - Thursday Sept. 15 - Friday
Registration 9:00-10:40
Opening & Keynote (I)
Keynote 1: Tim Cheng
Keynote 2: Ishih Tseng
Keynote (II)
Keynote 3: Phil Nigh
Keynote 4: Rob Aitken
10:40-11:00 Coffee Break 10:30-10:50 Coffee Break
Sessions A3, B3, C3
A3: (Invited) EDA Session
B3: Test for InFO and SoC
C3: Memory Test
12:20-13:30 Lunch Break 12:05-13:30 Lunch Break
Half-Day Tutorials
Automotive Test
3D-IC Test
Yield Learning
Sessions A1, B1, C1
A1: (Invited) Corporate Session I
B1: Analog/Mixed Signal Test
C1: Cell-Aware Test
Sessions A4, B4, C4
A4: (Invited) Fabless & IDM Session
B4: On-Chip Test Infrastructure
C4: Advanced Test Practices
14:45-15:00 Coffee Break 14:45-15:00 Coffee Break
Sessions A2, B2, C2
A2: (Invited) Corporate Session II
B2: Detection, Diagnosis, Debug
C2: Test for IoT and Automotives
Sessions A5, B5, C5
A5: (Invited) OSAT Session
B5: Verification & Fault Tolerance
C5: Embedded Tutorials

Sept. 13 – Wednesday, 13:30-16:50 am
Half-Day Tutorials

Session Chair: (TBD)
To be provided by speaker.
To be provided by speaker.

After a long period of technology hype, finally real 3D-stacked IC products containing through-silicon vias and micro-bumps (and also their interposer-based 2.5D-SIC variant) are hitting the market. Testing of 2.5D- and 3D-SICs is fraught with new test and design-for-test challenges, for which solutions are only emerging. The test challenges are the following. (1) Test flows: what to test for when? (2) Test content: do these stacked ICs bring new defects and faults and how do we test for those? (3) Test access: how do we pump in/out the test stimuli/responses into the dies and die stacks? In this tutorial, we present the fundamentals of 3D fabrication processes, defects, and fault modeling. We discuss test flows and present test-flow cost modeling and optimization. The tutorial covers the most promising solutions for pre-bond and post-bond (stack) testing, including advances in 3D probe technology, advanced 3D-DfT architectures and optimization, and the ongoing IEEE P1838 standardization effort for test access.
Erik Jan Marinissen is Principal Scientist at the world-renowned research institute imec in Leuven, Belgium, where he is responsible for the research on test and design-for-test, covering topics as diverse as TSV-based 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs. In addition, he is Visiting Researcher at Eindhoven University of Technology, the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven. Marinissen holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992), both from Eindhoven University of Technology. He is (co-)author of 250 journal and conference papers and (co-) inventor on fifteen granted US/EP patent families. Marinissen is recipient of the Most Significant Paper Awards at ITC 2008 and ITC 2010, Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability Workshop 1995 and the IEEE International Board Test Workshop 2002, the Most Inspirational Presentation Award at the IEEE Semiconductor Wafer Test Workshop 2013, the HiPEAC Tech Transfer Award 2015, and finalist for the National Instruments’ Engineering Impact Award 2017. He served as Editor-in-Chief of IEEE Std 1500 and as Founder and Chair (currently Vice-Chair) of the IEEE Std P1838 Working Group on 3D test access. Marinissen is founder of the workshops ‘Diagnostic Services in Network-on-Chips’ (DSNOC), DATE’s Friday 3D Integration, and the IEEE ‘International Workshop on Testing Three-Dimensional Integrated Circuits’ (3D-TEST). He has been Program Chair of DDECS 2002, ETS 2006, 3D-TEST 2009-15, and DATE 2013, and General Chair of ETW 2003, DSNOC 2007-08, 3DIW 2009-10, and serves on numerous conference committees, including ATS, DATE, ETS, ITC, ITC-Asia and VTS. He serves on the editorial boards of IEEE ‘Design & Test’ and Springer’s ‘Journal of Electronic Testing: Theory and Applications’. During the span of his career, Marinissen has supervised 35 international MSc and PhD students. He is a Fellow of IEEE and Golden Core Member of Computer Society. Marinissen presented numerous tutorials at conferences like 3DIC, 3D-ASIP, ATS, DATE, ETS, ETW, ITC, VTS.

To be provided by the speaker.
Wu-Tung Cheng (S’84–M’85–SM’90–F’00) received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1978 and 1982, respectively, and the Ph.D. degree in computer science from the University of Illinois at Urbana–Champaign, Urbana, IL, in 1985. From 1985 to 1990, he was with AT&T Bell Laboratories, Princeton, NJ, developing a test pattern generation system for digital circuits. From 1990 to 1993, he was a cofounder of CheckLogic System, Inc., and was the Vice President of Engineering, leading a team to develop commercial automatic test-generation products, which included FastScan, FlexTest, and DFTAdvisor. In 1993, CheckLogic was merged with Mentor Graphics Corporation, Wilsonville, OR. Since then, he has had various technical and management positions in design for test area at Mentor Graphics Corporation. He is currently a Chief Scientist and the director of Advanced Test Research, leading a team to develop new design-for-test solutions for future semiconductor quality and yield issues. He has published over 120 research papers in these areas and is the Coinventor of 30 patents. Dr. Cheng serves as a member of several technical program committees of workshops and conferences.

Sept. 14 – Thursday, 9:00-10:40 am
Keynote (I)

Session Chair: (TBD)
In this talk I will illustrate several types of Hardware Trojans and security threats they create, as well as opportunities of Trojan insertion in all steps of the design, fabrication, and testing processes. I will then discuss their defense mechanisms, verification techniques for Trojan detection and prevention, and test-specific need and challenges for hardware security.
K.-T. Tim Cheng received his Ph.D. in EECS from the University of California, Berkeley in 1988. He has been serving as Dean of Engineering and Chair Professor of ECE and CSE at Hong Kong University of Science and Technology (HKUST) since May 2016. He worked at Bell Laboratories from 1988 to 1993 and joined the faculty at Univ. of California, Santa Barbara in 1993 where he was the founding director of UCSB’s Computer Engineering Program (1999-2002), Chair of the ECE Department (2005-2008) and Associate Vice Chancellor for Research (2013-2016). His current research interests include hardware verification and security, design automation for photonics IC and flexible hybrid circuits, memristive memories, mobile embedded systems, and mobile computer vision. He has published more than 400 technical papers, co-authored five books, adviced 40+ PhD theses, and holds 12 U.S. Patents in these areas.
Cheng, an IEEE fellow, received 10+ Best Paper Awards from various IEEE and ACM conferences and journals. He has also received UCSB College of Engineering Outstanding Teaching Faculty Award. He served as Editor-in-Chief of IEEE Design and Test of Computers and was a board member of IEEE Council of Electronic Design Automation’s Board of Governors and IEEE Computer Society’s Publication Board.

To be provided by the speaker.
To be provided by the speaker.

Sept. 15 – Thursday, 9:00-10:30 am
Keynote (II)

Session Chair: (TBD)
To be provided by the speaker.
To be provided by the speaker.

To be provided by the speaker.
Rob Aitken is an ARM Fellow responsible for technology direction at ARM Research. He works on low power design, technology roadmapping, and next generation memories. He has worked on 15+ Moore’s law nodes and has published over 80 technical papers, on a wide range of topics. Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.

Sept. 14 – Thursday, 11:00-12:20 am
Plenary Panel

Panel Chair: Prof. Cheng-Wen Wu

Sept. 14 – Thursday, 13:30-14:45 pm
Session A1: (Invited) Corporate Session (I)

Session Chair: (TBD)

A1-1: To be designed…

A1-2: To be designed…

A1-3: To be designed…

Sept. 14 – Thursday, 13:30-14:45 pm
Session B1: Analog and Mixed-Signal Test

Session Chair: (TBD)

B1-1: Low-Distortion Signal Generation for Analog/Mixed-Signal Circuit Testing with Digital ATE
Masayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida and Haruo Kobayashi

B1-2: A Quick Jitter Tolerance Estimation Technique for Bang-bang CDRs
Yen-Long Lee and Soon-Jyh Chang

B1-3: Evaluation of Loop Transfer Function Based Dynamic Testing of LDOs
Mehmet Ince, Sule Ozev, Ender Yilmaz, Jae Woong Jeong and Leroy Winemberg

Sept. 14 – Thursday, 13:30-14:45 pm
Session C1: Cell-Aware Test

Session Chair: (TBD)

C1-1: (invited) The Role of Test in Advanced System Design – Challenges & Opportunities
Rob Knoth, Cadence

C1-2: Test Generation for Open and Delay Faults in CMOS Cells
Cheng-Hung Wu, Kuen-Jong Lee and Sudhakar M. Reddy, National Cheng-Kung Univ., Taiwan

C1-3: Cell-Aware Test Time Reduction by Using Switch-Level ATPG
Po-Yao Chuang, Cheng-Wen Wu and Harry H. Chen, National Tsing Hua Univ., Taiwan

Sept. 14 – Thursday, 15:00-16:40 pm
Session A2: (Invited) Corporate Session (II)

Session Chair: (TBD)

A2-1: To be designed…

A2-2: To be designed…

A2-3: To be designed…

Sept. 14 – Thursday, 15:00-16:40 pm
Session B2: Detection, Diagnosis, and Debugging

Session Chair: (TBD)

B2-1: GPU Accelerated Fault Dictionary Generation for the TRAX Fault Model
Matthew Beckler and Shawn Blanton, Carnegie Mellon Univ., USA

B2-2: Physical-aware Diagnosis of Multiple Interconnect Defects
Jing-Yu Chen, Po-Hao Chen, Chi-Lin Lee, Po-Wei Chen, and Chien-Mo Li, National Taiwan Univ., Taiwan

B2-3: A Run-Pause-Resume Silicon Debug Technique for Clock Domain
Shuo-Lian Hong and Kuen-Jong Lee, National Cheng-Kung Univ., Taiwan

B2-4: A Hybrid Concurrent Error Detection Scheme for Simultaneous Improvement on Probability of Detection and Diagnosability
Chih-Hao Wang and Tong-Yu Hsieh, National Sun Yat-Sen Univ., Taiwan

Sept. 14 – Thursday, 15:00-16:40 pm
Session C2: Test for IoT and Automotives

Session Chair: (TBD)

C2-1: A Dependable AMR Sensor System for Automotive Applications
Andreina Zambrano and Hans Kerkhoff

C2-2: An Automotive MP-SoC Featuring an Advanced Embedded Instrument Infrastructure for High Dependability
Hans G. Kerkhoff, Ghazanfar Ali, Hassan Ebrahimi, and Ahmed Ibrahim

C2-3: Symbiotic System Models for Efficient IOT System Design and Test
Cheng-Wen Wu, Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, and Chi Chen

C2-4: A Lightweight X-Masking Scheme for IoT-Designs
Daniel Tille, Benedikt Gottinger, and Ulrike Pfannkuchen

Sept. 15 – Friday, 10:50-12:05 am
Session A3: (Invited) EDA Session

Session Chair: (TBD)

A3-1: To be designed…

A3-2: To be designed…

A3-3: To be designed…

Sept. 15 – Friday, 10:50-12:05 am
Session B3: Test for InFO and SoC

Session Chair: (TBD)

B3-1: Fan-Out Wafer Level Chip Scale Package Testing
Hao Chen, Hung-Chih Lin, and Min-Jer Wang

B3-2: Testing-for-Manufacturing (TFM) for Ultra-thin IPD on InFO
Tang-Jung Chiu

B3-3: (invited) Test Strategy for Storage SoCs
Abhishek Bhattacharya and Ramesh Tekumalla

Sept. 15 – Friday, 10:50-12:05 am
Session C3: Memory Test

Session Chair: (TBD)

C3-1: Adaptive Block-Based Refresh Techniques for Mitigation of Data Retention Faults and Reduction of Refresh Power
Shyue-Kung Lu

C3-2: Software-Hardware-Cooperated Built-In Self-Test Scheme for Channel-Based DRAMs
Tsung-Fu Hsien, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, and Yung-Fa Chou

C3-3: Adapting an Industrial Memory BIST solution for testing CAMs
Jais Abraham, Uttam Garg, Glenn Colon-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, and Martin Keim

Sept. 15 – Friday, 13:30-14:45 pm
Session A4: (Invited) Fabless and IDM Session

Session Chair: (TBD)

A4-1: (invited) DFT Challenges and Solutions for Automotive ICs
Ying-Yen Chen, RealTek Semiconductor Corp, Taiwan
Abstract: Compared to consumer ICs, automotive ICs have more stringent requirement including extremely high test coverage, short failure analysis time and the ability of in-field test and diagnosis. In this presentation, we will describe the challenges we faced and the solutions we took in DFT aspect of automotive ICs.

A4-2: (invited) Multi-Pronged Strategy to Reduce Scan Test Cost at Advanced Process Nodes
Jianguo Ren, MediaTek Inc., Taiwan
Abstract: For advanced semiconductor processes, more and more fault models are required to improve chip quality, causing a dramatic rise in scan-related production test cost. We can address test cost reduction at three levels: design planning, chip implementation, and ATE execution. This talk will focus on chip implementation and ATE execution: (1) circuit modifications to increase scan shift frequency, and (2) constraining ATE timing sets to be speed-path and IR-drop aware. Adoption of these solutions has resulted in a 50% reduction of scan-related test cost across many products at MediaTek.

A4-3: (invited) What do we do to make system reliable?
Xinli Gu, Huawei Technologies, USA
Abstract: A reliable system requires an end-to-end planning, design, manufacturing test and maintenance for reliability. The reliability challenges for a large system come from the followings: 1) new designs and technologies which haven’t been fully tested in the field, 2) extremely large number of pieces of designs that no single individual can fully understand its reliability coverage, 3) 3rd party or legacy designs/parts used in the system, and 4) complicated system operation environment in customer field. This presentation will cover the reliability challenges and the best industrial practice, and promote research to work on the methodology for industrial system reliability.

Sept. 15 – Friday, 13:30-14:45 pm
Session B4: On-Chip Test Infrastructure

Session Chair: (TBD)

B4-1: Reconfigurable Access to On-Chip Infrastructure
Michael Kochte, Rafal Baranowski, and Hans-Joachim Wunderlich

B4-2: On the Effects of Real Time and Contiguous Measurement with a Digital Temperature and Voltage sensor
Yousuke Miyake, Yasuo Sato, and Seiji Kajihara

B4-3: Enhancing Security of Logic Encryption Using Embedded Key Generation Unit
Rajit Karmakar, Santanu Chattopadhyay, and Rohit Kapur

Sept. 15 – Friday, 13:30-14:45 pm
Session C4: Advanced Test Practices

Session Chair: (TBD)

C4-1: A Mathematical Model to assess the influence of parallelism in a Semiconductor Back-End Test Floor
Davide Appello, Mariapina Laurino, and Marco Pranzo

C4-2: A Full-Automatic Test System for Characterizing Large-Array Fine-Pitch Micro-Bump Probe Cards
Erik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Joerg Kiesewetter, Eric Hill, and Ken Smith

C4-3: Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints
Young-Woo Lee, Inhyuk Choi, Kang-Hoon Oh, James Jinsoo Ko, and Sungho Kang

Sept. 15 – Friday, 15:00-16:40 pm
Session A5: (Invited) OSAT Session

Session Chair: (TBD)

A5-1: (invited) To be designed
Wendy Chen, KYEC, Taiwan

A5-2: (invited) To be designed
Roger Huang, ASE, Taiwan

A5-3: (invited) To be designed
George Chang, Chroma (ATE), Taiwan

A5-4: (invited) A Probe Card Metrology Process Enabling Fast Feedback Loops to Reduce Operational and Maintenance Related cost
Martin Kunz, NanoFocus, Germany

Sept. 15 – Friday, 15:00-16:40 pm
Session B5: Verification and Fault Tolerance

Session Chair: (TBD)

B5-1: Assignment for Fault Tolerant Stochastic Computing with Linear Finite State Machines
Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki and Tomoo Inoue

B5-2: An Integrated Design Environment of Fault Tolerant Processors with Flexible HW/SW Solutions for Versatile Performance/Cost/Coverage Tradeoffs
Yi-Ju Ke, Yi-Chieh Chen and Ing-Jer Huang

B5-3: Speeding up Power Verification by Merging Equivalent Power Domains in RTL Design with UPF
Charles C.-H. Hsu and Charles H.-P. Wen

Sept. 15 – Friday, 15:00-16:30 pm
Session C5: Embedded Tutorials

Session Chair: (TBD)

C5-1: At-Speed Test Challenges for Giga-Size and Giga-Hertz Designs
Kun-Han (Hans) Tsai, Mentor Graphics, USA
Abstract: At-speed test is a must to ensure the high quality of today’s high performance ICs by screening out timing defects. This tutorial highlight the main challenges for testing today’s high performance designs with multiple cores and the state-of-art solutions in industrial designs.

C5-2: Deep Neural Network Design and Applications on Testing
Jin-Fu Li, National Central Univ., Taiwan

C5-3: To be designed
Charles Wen, National Chiao-Tung Univ., Taiwan