ITC-Asia 2017 Accepted Papers
Chih-Hao Wang and Tong-Yu Hsieh. A Hybrid Concurrent Error Detection Scheme for Simultaneous Improvement on Probability of Detection and Diagnosability
Masayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida and Haruo Kobayashi. Low-Distortion Signal Generation for Analog/Mixed-Signal Circuit Testing with Digital ATE
Daniel Tille, Benedikt Gottinger and Ulrike Pfannkuchen. A Lightweight X-Masking Scheme for IoT-Designs Shuo-Lian Hong and Kuen-Jong Lee. A Run-Pause-Resume Silicon Debug Technique for Clock Domain Crossing Interface Hao Chen, Hung-Chih Lin and Min-Jer Wang. Fan-Out Wafer Level Chip Scale Package Testing
Tang-Jung Chiu. Testing-for-Manufacturing (TFM) for Ultra-thin IPD on InFO
Yen-Long Lee and Soon-Jyh Chang. A Quick Jitter Tolerance Estimation Technique for Bang-bang CDRs
Cheng-Hung Wu, Kuen-Jong Lee and Sudhakar M. Reddy. Test Generation for Open and Delay Faults in CMOS Cells
Michael Kochte, Rafal Baranowski and Hans-Joachim Wunderlich. Trustworthy Reconfigurable Access to On-Chip Infrastructure
Davide Appello, Mariapina Laurino and Marco Pranzo. A Mathematical Model to assess the influence of parallelism in a Semiconductor Back-End Test Floor
Andreina Zambrano and Hans Kerkhoff. A Dependable AMR Sensor System for Automotive Applications Hans G. Kerkhoff, Ghazanfar Ali, Hassan Ebrahimi and Ahmed Ibrahim. An Automotive MP-SoC Featuring an Advanced Embedded Instrument Infrastructure for High Dependability Po-Yao Chuang, Cheng-Wen Wu and Harry H. Chen. Cell-Aware Test Time Reduction by Using Switch-Level ATPG
Shyue-Kung Lu. Adaptive Block-Based Refresh Techniques for Mitigation of Data Retention Faults and Reduction of Refresh Power
Tsung-Fu Hsien, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai and Yung-Fa Chou. Software-Hardware-Cooperated Built-In Self-Test Scheme for Channel-Based DRAMs
Cheng-Wen Wu, Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng and Chi Chen. Symbiotic System Models for Efficient IOT System Design and Test
Jing-Yu Chen, Po-Hao Chen, Chi-Lin Lee, Po-Wei Chen and Chien-Mo Li. Physical-aware Diagnosis of Multiple Interconnect Defects
Young-Woo Lee, Inhyuk Choi, Kang-Hoon Oh, James Jinsoo Ko and Sungho Kang. Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints
Rajit Karmakar, Santanu Chattopadhyay and Rohit Kapur. Enhancing Security of Logic Encryption Using Embedded Key Generation Unit
Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki and Tomoo Inoue. State Assignment for Fault Tolerant Stochastic Computing with Linear Finite State Machines
Yousuke Miyake, Yasuo Sato and Seiji Kajihara. On the effects of real time and contiguous measurement with a digital temperature and voltage sensor
Mehmet Ince, Sule Ozev, Ender Yilmaz, Jae Woong Jeong and Leroy Winemberg. Evaluation of Loop Transfer Function Based Dynamic Testing of LDOs
Jais Abraham, Uttam Garg, Glenn Colon-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine and Martin Keim. Adapting an Industrial Memory BIST solution for testing CAMs
Charles C.-H. Hsu and Charles H.-P. Wen. Speeding up Power Verification by Merging Equivalent Power Domains in RTL Design with UPF
Matthew Beckler and Shawn Blanton. GPU_Accelerated Fault Dictionary Generation for the TRAX Fault Model
Yi-Ju Ke, Yi-Chieh Chen and Ing-Jer Huang. An Integrated Design Environment of Fault Tolerant Processors with Flexible HW/SW Solutions for Versatile Performance/Cost/Coverage Tradeoffs